Library ieee;
Use ieee.std_logic_1164.all;

ENTITY PC IS
PORT(PCin,PCout,Clk          : IN std_logic;
bidir 						           : INOUT std_logic_vector(15 downto 0));
END PC;

Architecture PC_reg of PC is
begin
process(Clk)
VARIABLE PCval : std_logic_vector(15 downto 0);
begin
if rising_edge(Clk) then
	if PCin = '1' then
		PCval := bidir;
	elsif PCout = '1' then
	    bidir <= PCval;
	else
	    bidir <= "ZZZZZZZZZZZZZZZZ";
	end if;
end if;
end process;
end PC_reg;